1

Accelerating Deep Neural Network guided MCTS using Adaptive Parallelism
Click the Cite button above to demo the feature to enable visitors to import publication metadata into their reference management software.
Yuan Meng, Qian Wang, Tianxin Zu, Viktor Prasanna
PDF Cite Code
A Framework for Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform via on-chip Dynamic Tree Management
Click the Cite button above to demo the feature to enable visitors to import publication metadata into their reference management software.
Yuan Meng, Rajgopal Kannan, Viktor Prasanna
PDF Cite Code
Accelerator Design and Exploration for Deformable Convolution Networks
Click the Cite button above to demo the feature to enable visitors to import publication metadata into their reference management software.
Yuan Meng, Hongjiang Men, Viktor Prasanna
PDF Cite Code
Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform
Monte Carlo Tree Search (MCTS) methods have achieved great success in many Artificial Intelligence (AI) benchmarks. The in-tree …
Yuan Meng, Rajgopal Kannan, Viktor Prasanna
PDF Cite Code
Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform
FPGA Acceleration of Deep Reinforcement Learning Using On-chip Replay Management
A major bottleneck in parallelizing deep reinforcement learning (DRL) is in the high latency to perform various operations used to …
Yuan Meng, Zhang Chi, Viktor Prasanna
PDF Cite Code
FPGA Acceleration of Deep Reinforcement Learning Using On-chip Replay Management
Dynamap: Dynamic Algorithm Mapping Framework for Low Latency CNN Inference
Emerging CNNs have diverse per-layer computation characteristics including parallelism, arithmetic intensity, locality, and memory …
Yuan Meng, Sanmukh Kuppannagari, Rajgopal Kannan, Viktor Prasanna
PDF Cite
Dynamap: Dynamic Algorithm Mapping Framework for Low Latency CNN Inference
How to Avoid Zero-spacing in Fractionally-Strided Convolution? A Hardware-Algorithm Co-design Methodology
Fractionally Strided Convolution (FSC) is a key operation in popular image-based Deep Learning models, for example, CNN back …
Yuan Meng, Sanmukh Kuppannagari, Rajgopal Kannan, Viktor Prasanna
PDF Cite Code
How to Avoid Zero-spacing in Fractionally-Strided Convolution? A Hardware-Algorithm Co-design Methodology
How to Efficiently Train Your AI Agent? Characterizing and Evaluating Reep Reinforcement Learning on Heterogeneous Platforms
Click the Cite button above to demo the feature to enable visitors to import publication metadata into their reference management software.
Yuan Meng, Yang Yang, Sanmukh Kuppannagari, Rajgopal Kannan, Viktor Prasanna
PDF Cite
QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning Accelerators
Click the Cite button above to demo the feature to enable visitors to import publication metadata into their reference management software.
Yuan Meng, Sanmukh Kuppannagari, Rachit Rajat, Ajitesh Srivastava, Rajgopal Kannan, Viktor Prasanna
PDF Cite Code
Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms
Click the Cite button above to demo the feature to enable visitors to import publication metadata into their reference management software.
Yuan Meng, Sanmukh Kuppannagari, Viktor Prasanna
PDF Cite